/***********************************************************************/
/*                                                                     */
/*  FILE        :device.c                                              */
/*  DATE        :Fri, Jan 17, 2014                                     */
/*  DESCRIPTION :setting the standard I/O.                             */
/*  CPU GROUP   :64                                                    */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.19).    */
/*  NOTE:THIS IS A TYPICAL EXAMPLE.                                    */
/***********************************************************************/
/*********************************************************************
*
* Device     : M16C/64,65
*
* File Name  : device.c
*
* Abstract   : Setting the standard I/O.
*
* History    : 1.80  (2009-01-28)
*
* Copyright (C) 2009 (2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*********************************************************************/


#if defined(NC30)		/* NCxx */
	/* dummy */
#elif defined(NC77)
	#error "NC77 not supported"
#elif defined(NC79)
	#error "NC79 not supported"
#else
	#error "NC30, NC77, NC79 not defined"
#endif				/* NCxx */

#ifdef PSECTION
#pragma SECTION	program	_program_l
#endif


#define M16C

#include <stdio.h>

#ifdef MELPS7700

#ifdef __UART0__
#pragma EQU _porta  =   0x0e            /*                              */
#pragma EQU _pa_vct =   0x10            /*                        */
#pragma EQU _portb  =   0x0f            /*                              */
#pragma EQU _pb_vct =   0x11            /*                        */
#pragma EQU _mode1  =   0x30            /*                   */
#pragma EQU _brg1   =   0x31            /*                     */
#pragma EQU _sbuf1  =   0x32            /*                   */
#pragma EQU _cntr1_l =  0x34            /*                    */
#pragma EQU _cntr1_h =  0x35            /*                    */
#pragma EQU _rbuf1  =   0x36            /*                   */
#else /* UART1 : default */
#pragma EQU _porta  =   0x0a            /*                              */
#pragma EQU _pa_vct =   0x0c            /*                        */
#pragma EQU _portb  =   0x0b            /*                              */
#pragma EQU _pb_vct =   0x0d            /*                        */
#pragma EQU _mode1  =   0x38            /*                   */
#pragma EQU _brg1   =   0x39            /*                     */
#pragma EQU _sbuf1  =   0x3a            /*                   */
#pragma EQU _cntr1_l =  0x3c            /*                    */
#pragma EQU _cntr1_h =  0x3d            /*                    */
#pragma EQU _rbuf1  =   0x3e            /*                   */
#endif

#define TXEPTY  0x8                     /*            */
#define TE      0x1                     /*               */
#define TI      0x2                     /*            */
#define RE      0x4                     /*               */
#define RI      0x8                     /*               */

#define ACK     0x40
#define BUSY    0x20
#define FAULT   0x10
#define RESET   0x8
#define STROBE  0x4

#define TRUE    1

char _porta;
char _pa_vct;
char _portb;
char _pb_vct;
char _mode1;
char _brg1;
char _sbuf1;
char _cntr1_l;
char _cntr1_h;
char _rbuf1;

#ifdef CLOCK_16
#define	BRG96		51	/* f2 (16Mhz/1) / 16 /  9600 - 1 = 64	*/
#define CNTR96		0	/* f2					*/
#define	BRG48		103	/* f2 (16Mhz/1) / 16 /  4800 - 1 = 103	*/
#define CNTR48		0	/* f2					*/
#define	BRG24		25	/* f16(16Mhz/16)/ 16 /  2400 - 1 = 25	*/
#define CNTR24		1	/* f16					*/
#define	BRG12		51	/* f16(16Mhz/16)/ 16 /  1200 - 1 = 51	*/
#define CNTR12		1	/* f16					*/
#else
#define	BRG96		25	/* f2 (8Mhz/1)  / 16 /  9600 - 1 = 25	*/
#define CNTR96		0	/* f2					*/
#define	BRG48		51	/* f2 (8Mhz/1)  / 16 /  4800 - 1 = 51	*/
#define CNTR48		0	/* f2					*/
#define	BRG24		12	/* f16(8Mhz/16) / 16 /  2400 - 1 = 12	*/
#define CNTR24		1	/* f16					*/
#define	BRG12		25	/* f16(8Mhz/16) / 16 /  1200 - 1 = 25	*/
#define CNTR12		1	/* f16					*/
#endif
#endif	/* MELPS7700 */

#ifdef M16C

#ifdef	__R8C__

#ifdef __UART0__
#pragma ADDRESS _mode1		0A0H	/* UART0           */
#pragma ADDRESS _brg1		0A1H	/* UART0         */
#pragma ADDRESS _sbuf1		0A2H	/* UART0           */
#pragma ADDRESS _cntr1_l	0A4H	/* UART0      (L) */
#pragma ADDRESS _cntr1_h	0A5H	/* UART0      (H) */
#pragma ADDRESS _rbuf1		0A6H	/* UART0           */
#else /* UART1 : default */
#pragma ADDRESS _mode1		0A8H	/* UART1             */
#pragma ADDRESS _brg1		0A9H	/* UART1               */
#pragma ADDRESS _sbuf1		0AAH	/* UART1             */
#pragma ADDRESS _cntr1_l	0ACH	/* UART1      (L)     */
#pragma ADDRESS _cntr1_h	0ADH	/* UART1      (H)     */
#pragma ADDRESS _rbuf1		0AEH	/* UART1             */
#endif

#else // __R8C__

#if 0

#ifdef __UART0__
#pragma EQU _porta  =   0x3EC           /*                              */
#pragma EQU _pa_vct =   0x3EE           /*                        */
#pragma EQU _portb  =   0x3ED           /*                              */
#pragma EQU _pb_vct =   0x3EF           /*                        */
#pragma EQU _mode1  =   0x3A0           /*                   */
#pragma EQU _brg1   =   0x3A1           /*                     */
#pragma EQU _sbuf1  =   0x3A2           /*                   */
#pragma EQU _cntr1_l =  0x3A4           /*                    */
#pragma EQU _cntr1_h =  0x3A5           /*                    */
#pragma EQU _rbuf1  =   0x3A6           /*                   */
#else /* UART1 : default */
#pragma EQU _porta  =   0x3E8           /*                              */
#pragma EQU _pa_vct =   0x3EA           /*                        */
#pragma EQU _portb  =   0x3E9           /*                              */
#pragma EQU _pb_vct =   0x3EB           /*                        */
#pragma EQU _mode1  =   0x3A8           /*                   */
#pragma EQU _brg1   =   0x3A9           /*                     */
#pragma EQU _sbuf1  =   0x3AA           /*                   */
#pragma EQU _cntr1_l =  0x3AC           /*                    */
#pragma EQU _cntr1_h =  0x3AD           /*                    */
#pragma EQU _rbuf1  =   0x3AE           /*                   */
#endif

#else // 0

#ifdef __UART0__
#pragma EQU _porta  =   0x3EC           /* Port P6 Register                           */
#pragma EQU _pa_vct =   0x3EE           /* Port P6 Direction Register                 */
#pragma EQU _portb  =   0x3ED           /* Port P7 Register                           */
#pragma EQU _pb_vct =   0x3EF           /* Port P7 Direction Register                 */
#pragma EQU _mode1  =   0x248           /* UART0 Transmit/Receive Mode Register       */
#pragma EQU _brg1   =   0x249           /* UART0 Bit Rate Register                    */
#pragma EQU _sbuf1  =   0x24A           /* UART0 Transmit Buffer Register             */
#pragma EQU _cntr1_l =  0x24C           /* UART0 Transmit/Receive Control Register 0  */
#pragma EQU _cntr1_h =  0x24D           /* UART0 Transmit/Receive Control Register 1  */
#pragma EQU _rbuf1  =   0x24E           /* UART0 Receive Buffer Register              */
#else /* UART1 : default */
#pragma EQU _porta  =   0x3E8           /* Port P4 Register                           */
#pragma EQU _pa_vct =   0x3EA           /* Port P4 Direction Register                 */
#pragma EQU _portb  =   0x3E9           /* Port P5 Register                           */
#pragma EQU _pb_vct =   0x3EB           /* Port P5 Direction Register                 */
#pragma EQU _mode1  =   0x258           /* UART1 Transmit/Receive Mode Register       */
#pragma EQU _brg1   =   0x259           /* UART1 Bit Rate Register                    */
#pragma EQU _sbuf1  =   0x25A           /* UART1 Transmit Buffer Register             */
#pragma EQU _cntr1_l =  0x25C           /* UART1 Transmit/Receive Control Register 0  */
#pragma EQU _cntr1_h =  0x25D           /* UART1 Transmit/Receive Control Register 1  */
#pragma EQU _rbuf1  =   0x25E           /* UART1 Receive Buffer Register              */
#endif

#endif // 0

#endif  // __R8C__

#define TXEPTY  0x8                     /*            */
#define TE      0x1                     /*               */
#define TI      0x2                     /*            */
#define RE      0x4                     /*               */
#define RI      0x8                     /*               */

#define ACK     0x40
#define BUSY    0x20
#define FAULT   0x10
#define RESET   0x8
#define STROBE  0x4

#define TRUE    1

char _porta;
char _pa_vct;
char _portb;
char _pb_vct;
char _mode1;
char _brg1;
char _sbuf1;
char _cntr1_l;
char _cntr1_h;
char _rbuf1;

#define	BRG192		31	/* f1(10Mhz/1) / 16 / 19200 - 1 = 31	*/
#define CNTR192		0	/* f1					*/
#define	BRG96		64	/* f1(10Mhz/1) / 16 /  9600 - 1 = 64	*/
#define CNTR96		0	/* f1					*/
#define	BRG48		129	/* f1(10Mhz/1) / 16 /  4800 - 1 = 129	*/
#define CNTR48		0	/* f1					*/
#define	BRG24		31	/* f8(10Mhz/8) / 16 /  2400 - 1 = 31	*/
#define CNTR24		1	/* f8					*/
#define	BRG12		64	/* f8(10Mhz/8) / 16 /  1200 - 1 = 64	*/
#define CNTR12		1	/* f8					*/

#endif	/* M16C */

/*******************************************************************************
*
* init_dev 
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*     : Version 2.00.00
* 	    Version 2.01.00
*		        
*
*        init_dev --           
*
*        status = init_dev( stream, mode )
*
*           #include <stdio.h>
*           FILE *stream                  
*           int  mode;             
*           int  status;               
*
*                                          
*
*                           
*
*******************************************************************************/

int init_dev( stream, mode )
FILE _far *stream;
int  mode;
{
    if ( mode != _TEXT && mode != _BIN )
        return  EOF;
    stream->_mod = mode;
    return  TRUE;
}


/*******************************************************************************
*
* speed 
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*     : Version 2.00.00
* 	    Version 2.01.00
*		        
* 	    Version 3.00.00
*		    ,        
*
*        speed --          
*
*        status = speed( rate, bit, parity, stop );
*
*           #include <stdio.h>
*           int  rate;               
*           int  bit;               
*           int  parity;            
*           int  stop;                 
*           int  status;               
*
*                                          
*
*                                        
*                 
*
*******************************************************************************/

int speed( rate, bit, parity, stop )
int  rate;                              /*             */
int  bit;                               /*              */
int  parity;                            /*              */
int  stop;                              /*           */
{
    int mode;                           /*              */

    _cntr1_h = NULL;                    /*            */
    switch( rate ) {                    /*          */
	case _192:
	    _brg1 = BRG192;
            _cntr1_l = CNTR192;
            break;
        case _96:
            _brg1 = BRG96;
            _cntr1_l = CNTR96;
            break;
        case _48:
            _brg1 = BRG48;
            _cntr1_l = CNTR48;
            break;
        case _24:
            _brg1 = BRG24;
            _cntr1_l = CNTR24;
            break;
        case _12:
            _brg1 = BRG12;
            _cntr1_l = CNTR12;
            break;
        default:
            return EOF;
    }
    switch( bit ) {                     /*         */
        case _B8:
            mode = 0x5;
            break;
        case _B7:
            mode = 0x4;
            break;
        default:
            return EOF;
    }
    switch( parity ) {                  /*         */
        case _PN:
            break;
        case _PE:
            mode |= 0x60;
            break;
        case _PO:
            mode |= 0x40;
            break;
        default:
            return EOF;
    }
    switch( stop ) {                    /*            */
        case _S1:
            break;
        case _S2:
            mode |= 0x10;
            break;
        default:
            return EOF;
    }
    _mode1 = mode;
    return  TRUE;
}

/*******************************************************************************
*
* _sget 
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*     : Version 2.00.00
* 	    Version 2.01.00
*		        
*
*        _sget --             
*
*        data = _sget( void );
*
*           int  data;          
*
*                                        
*              
*
*                      
*
*******************************************************************************/


int _sget( )                            /*               */
{
    int  data;

    _cntr1_h = _cntr1_h | RE;           /*             */
#ifndef SIMULATOR
    while ( !( _cntr1_h & RI ) ) ;      /*                      */
#endif
    data = _rbuf1;
    return data;
}


/*******************************************************************************
*
* _sput 
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*     : Version 2.00.00
* 	    Version 2.01.00
*		        
*
*        _sput --             
*
*        status = _sput( c );
*
*           int  c;               
*           int  status;           
*
*                                      
*
*                      
*
*******************************************************************************/


int _sput( c )                          /*               */
int c;
{
    int i;

    _cntr1_h = _cntr1_h | TE;           /*             */
#ifndef SIMULATOR
    while ( !( _cntr1_h & TI ) ) ;      /*                         */
#endif
    _sbuf1 = c;
    if ( _cntr1_h & 0xf0 )
        return EOF;                     /*        */
    return  TRUE;
}


/*******************************************************************************
*
* _pput 
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*     : Version 2.00.00
* 	    Version 2.01.00
*		        
*
*        _pput --                    
*
*        status = _pput( c );
*
*           int  c;               
*           int  status;           
*
*                                      
*
*                             
*
*******************************************************************************/

int _pput( c )                          /*                      */
int c;
{
    int  i;

    if ( _porta & FAULT )
        return EOF;
    while ( !( _porta & BUSY ) ) ;      /* BUSY               */
    _portb = c;
    for ( i = 0 ; i < 10 ; i++ ) ;      /*      */
    _porta = RESET;                     /* STROBE     */
    for ( i = 0 ; i < 10 ; i++ ) ;      /*      */
    _porta = RESET | STROBE;            /* STROBE   */
    while ( _porta & ACK ) ;            /* ACK   */
    if ( _porta & FAULT )
        return EOF;
    else
        return TRUE;
}



/*******************************************************************************
*
*                     
*
* Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
* and Renesas Solutions Corporation. All rights reserved.
*
*
*******************************************************************************/
